| United States Patent | 6,419,148 |
| Waxler ,   et al. | July 16, 2002 |
A system and method for forming bumps on an integrated circuit including a scanning direct laser imager employed to selectably expose a photosensitive layer deposited on an integrated circuit substrate, thereby to define regions overlying selected portions of the substrate, a developer developing said photosensitive layer to form apertures in the photosensitive layer at the defined regions, and a solder applicator applying a solder composition to the apertures to define solder bumps on the integrated circuit at selected portions thereof.
| Inventors: | Waxler; Scott Steven (North Reading, MA); Zemer; Dan (Rehovot, IL) |
| Assignee: | Orbotech Ltd. (Yavne, IL) |
| Appl. No.: | 767645 |
| Filed: | January 23, 2001 |
| Current U.S. Class: | 228/214; 228/14; 219/121.7 |
| Intern'l Class: | B23K 026/00 |
| Field of Search: | 228/259,6.1,6.2,118,179.1,180.1,180.21,180.22,188,189,214,14,13 219/121.68,121.69,121.75,121.79,121.7 |
| 5024372 | Jun., 1991 | Altman et al. | 228/248. |
| 5118027 | Jun., 1992 | Braun et al. | 228/180. |
| 5161257 | Nov., 1992 | Arensdorf et al. | |
| 5293006 | Mar., 1994 | Yung | 174/261. |
| 5323947 | Jun., 1994 | Juskey et al. | 228/56. |
| 5447264 | Sep., 1995 | Koopman et al. | 28/563. |
| 5539153 | Jul., 1996 | Schwiebert | 174/260. |
| 5672542 | Sep., 1997 | Schwiebert | 437/183. |
| 5738269 | Apr., 1998 | Masterton | 228/248. |
| 5829668 | Nov., 1998 | George et al. | 228/254. |
| 5938106 | Aug., 1999 | Pierson | 228/246. |
| 5946590 | Aug., 1999 | Satoh. | |
| 6053397 | Apr., 2000 | Kaminski | 228/254. |
| 6053398 | Apr., 2000 | Iizuka et al. | 228/254. |
| 6056191 | May., 2000 | Brouillette et al. | 228/254. |
| 6085968 | Jul., 2000 | Swindlehurst et al. | 228/254. |
| 6093476 | Jul., 2000 | Horiuchi et al. | |
| 6109507 | Aug., 2000 | Yagi et al. | 228/180. |
| Foreign Patent Documents | |||
| WO 00/02424 | Jan., 2000 | WO. | |
Analog Devices, "Designing with BGA: Surface Mount Assembly Recommendations for the 2106x Plastic Ball Grid Array (PBGA) Package", 3 pages. (http://www.analog.com/industry/dsp/bga/bgadesig.html) No Date Avail. Li Li and B. Yeung, "Wafer Level and Flip Chip Design Through Solder Prediction Models and Validation" (Abstract), Motorola Inc., 2000, 2 pages. (http://www.me.gatech.edu/mechatronics2000/Abstracts/245.htm). J. Titus, "How Do Manufacturers Inspect BGAs?", Test & Measurement World, Feb. 1999, 6 pages. (http://www.tmworld.com/articles/bga_0299.htm). U.S.S.N. 09/798,160, entitled Scaling and Registration Calibration Especially In Printed Circuit Board Fabrication, filed Nov. 8, 2000. Fujitsu Tohoku Electronics Ltd., "Design Rule of Solder-Bump (150mm Wafer)", 1997, 2 pages. (http://www.fujitsu.co.jp/hypertext/fte/english/bump_s1.htm). J. Franka et al., "Tap Resource: Solder Bump Technology: Present and Future", Semiconductorfabtech.com, 10 pages. No Date Avail. (http://www.semiconductorfabtech.com/features/tap/articles/02.289.html). Karl Suss, "Photolithography for Thin Film MCMs", 5 pages. (http://194.174.202.134/sitemap/photolith_thin_film.htm) No Date Avail. Research International Chipflo Ovens, "ChipFlo Series: BGA Solder Ball Attachment Convection Ovens", 3 pages. No Date Avail. (http://www.research-intl.com/products/chipflo.html). Orbotech, "Automated Optical Inspection Solutions", 2 pages. (http://www.orbotech.com/products/pcb/aoi,html) No Date Avail. Cognex, "BGA II Inspection Package: Machine Vision for Inspecting Ball Grid Arrays", 2000, 3 pages. (http://www.cognex.com/marketing/products/prod_bga.asp). G.E. McGuire, "Development of Liftoff Process for Patterning of Magnetic and other Materials", MCNC, 4 pages. No Date Avail (http://www.phys.ulf.edu/.about.nanoscale/reports/yearl/liftoff.html). UW-MEMS-DXRL Micromachining, "Deep X-Ray Lithography and Electrodeposition Micromachining", 4 pages. No Date Avail (http://www.mems.engr.wisc.edu/DXRL.html). R. Leitgeb, "Photolithography", Sep. 29, 1998, one page. (http://www.-rpl.stanford.edu/RPL/htmls/mesoscopic/processes/ photolithography.html). "Positive and Negative Photoresist", one page. No Date Avail (http://www.ece.gatech.edu/research/lab/vc/theory/PosNegRes.html). Chipscale Review, "Effects of Print Parameters", Jul.-Aug. 1999, 10 pages. (http://www.chipscalereview.com/chipscalen2/9907/rechforums3.htm). "Chapter E: Ball Grid Array Techn.", 8 pages. No Date Avail (http://extra/ivf.se/ngl/E-BGA/ChapterE2,htm). R.H. Estes, "Technology Trends: Solderless Polymer Bump Process For Flip Chips", U.S. Tech Interactive, 1996, 6 pages. No Date Avail (http://www.us-tech.com/sept96/spftrspftr002.htm). J. Baliga, "Ball Grid Arrays: The High Pincount Workhorse", Semiconductor International, Sep. 1999, 6 pages. (http://209.67.253.149/semiconductor/issues/issues/1999/sep99/docs/ feature2.asp). "Design and Assembly Process Implementation for BGAs", Working Draft, IPC-7095, IPC, Apr. 1999, 105 pages. N.C. Lee, "The Use of Solder as an Area-Array Package Interconnect",Chipscale Review, Sep.-Oct. 1999, 8 pages. (http://www.chipscalereview.com/chipscalen2/9910/featured1.htm). |