| United States Patent | 6,426,478 |
| Yoo | July 30, 2002 |
A process for planarization of a silicon wafer is described together with apparatus for implementing it. The process planarizes by directing a high-energy, pulsed laser beam in a direction parallel to the wafer surface while the wafer is rotating. The height of the beam relative to the wafer is carefully controlled thereby enabling the removal of all material above the lower edge of the beam to be removed from the wafer through laser ablation. The method works equally well for removal of metal (as in planarization of damascene wiring) or dielectric (as in planarization of conventional wiring). Once all excess material has been removed (typically requiring about 60 seconds) additional operation of the process does no harm so neither end point detection nor precise control of process time are required.
| Inventors: | Yoo; Chue-San (Hsin-chu, TW) |
| Assignee: | Taiwan Semiconductor Manufacturing Company (Hsin-Chu, TW) |
| Appl. No.: | 839701 |
| Filed: | April 23, 2001 |
| Current U.S. Class: | 219/121.65; 219/121.82; 219/121.73 |
| Intern'l Class: | B23K 026/02 |
| Field of Search: | 438/626,662,600,601 427/555 445/50 216/56 219/121.6,121.73,121.78,121.79,121.82,121.65 |
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